During the design of an integrated circuit (IC) (e.g. application specific integrated circuit (ASIC) or system-on-chip (SOC)), design for test (DFT) and automatic test pattern generation (ATPG) methodologies are typically used to develop tests that, when applied to the IC, can detect potential failures of the IC as a whole. DFT and other design methodologies can also include building mission mode capabilities into an existing IC design. As used herein, mission mode refers to operations that occur when the IC is in its functional environment, as opposed to tests that are performed during manufacturing or when a device is first being powered up. This could be a run time application of test, for example. During mission mode and/or in safety critical applications, functional logic is taken offline and tested to detect issues during functional operation. Mission mode tests are typically limited to those capable of being performed in a very small window of time so as not to interfere with functional operation. This very small window of time cannot be met when data streams are loaded from off-chip sources. Also, mission mode tests must have a very fine granularity. This means that mission mode tests must be individually run on very small portions of the design to avoid impacting functional operations. This is a much finer granularity of testing than manufacturing tests during which the entire chip or large portions of the chip are tested at once.
Conventional techniques for embedding mission mode and other test capabilities into an IC significantly increase the area, power, and complexity of the entire system. For analog and digital parts common in many applications such as in the automotive industry, this significant logic increase or packaging change for a design can make these techniques unusable or push the design out of a profitable price point in its market.